1. Field of the Invention
The present invention relates to a memory system including a memory module having a plurality of memory devices. More particularly, the present invention relates to a memory system capable of controlling interface timing for the memory devices by storing timing control information in a memory information storage unit.
This application claims the benefit of Korean Patent Application No. 10-2004-0085381, filed on Oct. 25, 2004, the disclosure of which is incorporated by reference herein in its entirety.
2. Description of the Related Art
The performance of computer systems has improved over time, and along with this improvement has come changes in the design of memory systems. Most memory systems now include a plurality of memory modules, and most current memory modules include a plurality of memory devices. Conventional memory modules include Single In-line Memory Modules (SIMMs), Dual In-line Memory Modules (DIMMs), and Fully Buffered DIMMs (FBDIMMs).
A SIMM is a small printed circuit board on which at least one Random Access Memory (RAM), such as a Dynamic Random Access Memory (DRAM) or a Synchronous Dynamic Random Access Memory (SDRAM), chip is installed. The SIMM also includes pins that facilitate connection to a motherboard. A DIMM, which usually includes two SIMMs, also includes a plurality of RAM chips attached to a small printed circuit board and motherboard connection pins.
Conventional SIMMs typically read/write 32-bit wide data words and are thus often used in systems having 72 pin connectors. DIMMs typically read/write 64-bit wide data words and are used in systems having 168 pin connectors. Contemporary SDRAMs read/write 64-bit wide data words, so an SDRAM requires at least two SIMMs or a DIMM.
Conventional DIMMs are controlled by a memory controller external to the DIMM. In an exemplary system, a northbridge connected to a CPU acts as the memory controller. However, use of an external controller reduces the operation speed and limits performance of the DIMM.
An FBDIMM is a memory module developed to solve this problem. The FBDIMM has a controller installed in the memory module and adapted to control the operation of the memory module, including perhaps an Advanced Memory Buffer (AMB).
Since a plurality of memory devices are used in a memory module (particularly a DIMM or FBDIMM), and a plurality of memory modules are used in a memory system, it is necessary to initialize and set the timing of the memory modules, and the memory devices in each memory module, in order to properly read/write data to/from the memory modules in a memory system.
Conventionally, memory information, which includes memory initialization and timing information, is stored in a memory information storage unit such as a Serial Presence Detect (SPD) associated with a memory module. A memory controller will collect memory information stored in the SPD, and will then use the collected memory information to initialize and set the timing of the memory module when the memory controller initializes or tests the memory module.
The SPD, which stores memory information regarding the memory module and/or the memory devices, is located in the memory module. Information stored in the SPD includes all information regarding the memory module, such as speed, voltage, row/column address, refresh rate, AC parameters (clock cycle time (tCC), CAS delay time (tCL), RAS-CAS delay time (tRCD), row precharge time (tRP), etc.), and the producer of the memory module and/or memory devices.
FIG. 1 is a block diagram of an exemplary memory system including a memory module.
Memory system 100 shown in FIG. 1 includes CPU 110, memory controller 130, interface controller 150, and memory module 170. Interface controller 150 reads memory information M_INF stored in memory information storage unit 171 located in memory module 170 and then provides memory information M_INF to memory controller 130. Memory controller 130 stores memory information M_INF received from interface controller 150 in an internal memory timing register, initializes memory module 170 using memory information M_INF, and then sets the timing of the memory module. Thereafter, memory controller 130 provides memory signal M_SIG, including clock signal CLK, command signal CMD, address signal ADD, data strobe signal DQS, etc., to memory devices 179-1 through 179-8.
In a computer system, memory controller 130 can be implemented in a northbridge (NB), which connects the memory module, an Accelerated Graphics Port (AGP), and Peripheral Component Interconnect (PCI) buses to a CPU. Interface controller 150 can be implemented in a southbridge (SB) for controlling Integrated Drive Electronics (IDE) buses, Universal Serial Buses (USB's), plug and play support, a keyboard/mouse controller, power management, etc.
In the computer system, if the southbridge reads memory information from memory information storage unit 171 and requests an interrupt to the northbridge, the northbridge stops its current processing operation in response to the interrupt request, receives the memory information from the southbridge, stores the received memory information in its internal memory timing register, and then resumes its previous operation.
However, since memory module 170 is initialized and the memory timing is set using the memory timing information stored in external memory controller 130 in conventional memory system 100, a relatively long time is required to initialize the memory module, and controlling the interface timing of the memory device is difficult.
Since the recent development of various memory devices, a memory module must be able to use various memory devices, each with different interface timings such as set-up times and hold times, which makes controlling the memory module more difficult. Therefore, it is necessary to appropriately control different interface timings to prevent errors in a memory system.